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[VHDL-FPGA-Verilog] fft_gen

Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: | Size: 6144 | Author: Jayesh | Hits:

[VHDL-FPGA-Verilog] Debouncer_Ver2

Description: super fast debounce button on vhdl, xilinx xc
Platform: | Size: 1024 | Author: Terente | Hits:

[VHDL-FPGA-Verilog] Wiley.FPGA.Prototyping.by.VHDL.Examples.Xilinx.Sp

Description: Wiley,FPGA Prototyping by VHDL examples Spartan 3 version,Pong Chu,
Platform: | Size: 17548288 | Author: lefteris | Hits:

[VHDL-FPGA-Verilog] s3ask_ddr2

Description: DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
Platform: | Size: 2612224 | Author: Joe Zhu | Hits:

[VHDL-FPGA-Verilog] Bch15_5

Description: The attached file consists of implimentation of BCH codes in VHDL programming using XILINX software. This code will reduce the no. of gates requirement.
Platform: | Size: 13312 | Author: babi | Hits:

[Embeded-SCM Develop] afifo_0916

Description: 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
Platform: | Size: 154624 | Author: 范小虎 | Hits:

[Embeded-SCM Develop] rs232

Description: rs232 interface for xilinx spartan 3e
Platform: | Size: 8192 | Author: MILIND | Hits:

[VHDL-FPGA-Verilog] FFT

Description: fft implementation in fpga using vhdl xilinx
Platform: | Size: 894976 | Author: prabin | Hits:

[VHDL-FPGA-Verilog] SDRAMController

Description: xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
Platform: | Size: 128000 | Author: 陈俊 | Hits:

[Software Engineering] lcd_controller

Description: LCD controller 320x240 XC95144, building Xilinx ISE 6.0 Platform VHDL.
Platform: | Size: 4448256 | Author: Meke | Hits:

[Other] xilinx

Description: xilinx中文培训材料，非常好的FPGA学习资料-xilinx Chinese language training materials, a very good learning materials FPGA
Platform: | Size: 3704832 | Author: 小金 | Hits:

[VHDL-FPGA-Verilog] liushuideng

Description: 基于XILINX公司FPGA的流水灯代码，采用硬件描述语言VHDL-XILINX' s FPGA-based water lamp code, using hardware description language VHDL
Platform: | Size: 1103872 | Author: zhushiyong315 | Hits:

[VHDL-FPGA-Verilog] usb_fpga_1_2_latest.tar

Description: USB2.0的FPGA内核，使其可以通过FPGA控制CY公司出品的CY7C68013USB微控制器，对USB设备进行读写操作。-• Xilinx Spartan-3 XC3S400 FPGA • High-Speed (480 MBit/s) USB interface via Mini-USB connector (B-type) • Cypress CY7C68013A/14A EZ-USB-Microcontroller • 60 General Purpose I/O s (GPIO): ◦ 52 FPGA GPIO s ◦ 8 EZ-USB FX2 GPIO s (4 if Flash option is installed)
Platform: | Size: 328704 | Author: 赵恒 | Hits:

[VHDL-FPGA-Verilog] lcd_test

Description: Xilinx Spartan-3E实验板上基于verilog控制lcd屏幕A到Z反复轮转显示。-Xilinx Spartan-3E verilog based test control board lcd screen A to Z repeated rotary display.
Platform: | Size: 999424 | Author: 陈海凯 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL语言很严谨，通过对他的学习，编程思维更严谨！这个是很好的VHDL的总结内容，很好对于初学者！-VHDL language is very precise, through his learning, programming, more rigorous thinking! This is a good summary of the contents of VHDL, very good for beginners!
Platform: | Size: 454656 | Author: 周思源 | Hits:

[VHDL-FPGA-Verilog] mdf-code-xilinx

Description: median filter code in VHDl
Platform: | Size: 486400 | Author: ravitikkam | Hits:

[VHDL-FPGA-Verilog] RGB-YUV

Description: VHDL xilinx RGB2YUV for LEARN
Platform: | Size: 44032 | Author: wei | Hits:

[VHDL-FPGA-Verilog] Demo-Design-for-Kit-Board

Description: 基于XIlinx FPGA 开发板的一些经典参考设计-Demo Design for the Starter Kit Board of Xilinx FPGA
Platform: | Size: 5622784 | Author: saladin | Hits:

[source in ebook] Xilinx-ISE-10.1-Quick-Start-Tutorial

Description: VHDL Xilinx ISE 10.1 Quick Start Tutorial
Platform: | Size: 498688 | Author: simaozil | Hits:

[VHDL-FPGA-Verilog] Half-Adder

Description: xilinx ISE平台提供1位半加法器，模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)
Platform: | Size: 21504 | Author: DanCerv | Hits:
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